Components

An 8-bit adder that computes every carry from generate/propagate flags in two gate levels per group, instead of rippling bit by bit.

A 4-bit encoder and matching corrector: three parity bits let the receiver locate and flip any single corrupted code bit.

Drives four seven-segment digits over one shared bus: a scan counter, a nibble mux, and a single hex decode table with one-hot digit enables.

An 8-bit maximal-length LFSR in the Galois form: the feedback XORs sit inside the shift path instead of feeding bit zero.

A five-sample voting debouncer: the output follows the 3-of-5 majority, so isolated spikes are rejected and short dropouts are bridged.

A 16-bit phase accumulator that ticks at an average rate of step/65536 per clock: fractional rate division no plain counter can deliver.

Turn an 8-bit level into a 1-bit pulse-density stream with one accumulator: the carry out is the entire output stage.

Stream stereo 16-bit samples over three wires: bit clock, word select, and MSB-first serial data with the standard one-bit delay.

The standard CRC-32 one byte per clock: eight reflected polynomial steps unrolled into a single cycle's worth of XOR logic.

Drive an addressable LED over one wire: 24 GRB bits encoded as pulse widths, closed by the low latch gap.

A fully combinational 2x2 int8 matrix multiply: eight multipliers and four adders answering in a single step, the smallest slice of an AI accelerator's core operation.

A 4x4 int8 matrix multiply spread over three pipeline stages: 64 multipliers and 16 adder trees, accepting a new matrix pair every clock cycle.

Standards-correct 640x480 VGA timing from two counters and a handful of comparators, painting the classic eight color bars.