Learn

Learn what hardware description really means — parallel circuits, not sequential programs — through binary numbers, logic gates, two's complement, and Karnaugh-map simplification.

Write complete components from the first line to the last — declare interfaces with ports, swap implementations behind them, and use the three port directions correctly.

Declare wires of your own and give them honest types — the logic values and driver resolution, multi-bit vectors with indexing and slices, and the numeric types and constants that put real numbers on wires.

The operator toolbox for vectors: bitwise logic and reductions, concatenation and replication, and arithmetic with explicit width and sign handling.

Master the always-on assignments that wire circuits together outside any procedural block — plain, conditional, and selected — and see why the order of statements in a file changes nothing.

Step inside the process and the always block — the fenced region where statements run in order. Learn the default-first idiom, variables for step-by-step computation, and what wakes a block back up.

Make decisions inside procedural blocks with if and case statements, keep every path latch-free, and finish every case so synthesis builds exactly the logic you meant.

Build the standard combinational components every design leans on — multiplexers, decoders, encoders, display drivers, and tri-state buses — and choose the right coding style for each one.

Learn to read and write the self-checking benches that grade every design on this platform — DUT instantiation, stimulus timing, assertions that echo expected versus actual, and the wait statements that sequence it all.

Look inside the simulator: the event-driven loop that runs your designs, delta cycles, why signal and variable updates follow different rules, and how concurrent processes really communicate.

Master the conversion chains between raw vectors, unsigned and signed readings, and integers — numeric_std in VHDL, casting in SystemVerilog — and make every width and sign change explicit and correct.

Open the box behind the + operator: build adders from gates, chain them into multi-bit slices, shift by a signal amount, subtract with the same adder, flag overflow honestly, and assemble an ALU.

Cross from combinational to sequential design — build the storage elements that remember: the latch you avoid, the flip-flop you trust, and registers with resets, enables, and edge detection.

Compose designs out of designs — instantiate sub-units by name and by position, make them width-configurable with generics and parameters, generate repeated structure with one loop, and manage the binding and the wiring as the tree grows.

Design Moore and Mealy state machines, compare coding styles, and build FSMs with datapaths for real-world digital systems.