From your first circuit to a working FPGA system.
Work with binary numbers, logic gates, two's complement, and Karnaugh maps.
Define component interfaces, choose port directions, and write alternative implementations.
Declare signals, index and slice vectors, and choose signed or unsigned numeric types.
Combine vectors with logic, concatenation, shifts, arithmetic, and comparisons.
Describe combinational logic with concurrent assignments and conditional selection.
Write procedural blocks with default assignments, intermediate calculations, and sensitivity lists.
Use if statements, case statements, and loops without inferring unintended latches.
Build multiplexers, decoders, encoders, display drivers, and tri-state buses.
Drive test inputs, control simulation timing, and check expected outputs with assertions.
Trace event scheduling, delta cycles, and signal updates between concurrent processes.
Convert between vectors and integers while handling signedness, extension, and truncation.
Build adders, shifters, and an ALU, then handle fixed-point rounding and saturation.
Compare latches and flip-flops, then build registers with resets, enables, and edge detection.
Connect submodules, configure their widths, and generate repeated hardware.
Build binary, up/down, mod-N, Gray, ring, and Johnson counters.
Build delay lines, serial-parallel converters, pseudorandom sequence generators, and CRC circuits.
Organize data with enumerations, arrays, records, and structs, and control their bit layout.
Design Moore and Mealy state machines, compare coding styles, and connect FSMs to datapaths.
Reuse logic with functions, procedures, and tasks, and share definitions across files.
Combine counters, registers, and FSMs into debouncers, PWM generators, timers, and arbiters.
Pipeline arithmetic, align parallel paths, and handle stalls with ready/valid handshakes.
Test with files and reproducible random stimulus, measure functional coverage, and debug waveforms.
Infer RAM and ROM, and build register files and synchronous FIFOs.
Map RTL to FPGA resources, calculate setup and hold slack, write timing constraints, and inspect routed timing reports.
Handle metastability with level and pulse synchronizers, and synchronize reset release in each clock domain.
Transfer data between clock domains with request/acknowledge handshakes, Gray counters, and asynchronous FIFOs.
Build UART, SPI, and I2C interfaces, then connect on-chip blocks with AXI-Stream and APB.
Organize testbenches into drivers, monitors, and scoreboards, with race-free checks and assertions.
Practise retrieval across the whole course: mixed drills, a FIFO traced by hand, design questions with no code, and timed attempts at exercises you have built.