sequential component

Galois LFSR

Open in playground

An LFSR steps through a long, repeatable sequence of patterns using almost no hardware. This one is the Galois form of the classic 8-bit maximal-length generator, polynomial x^8 + x^6 + x^5 + x^4 + 1. Seeded with 0x01, it visits all 255 nonzero states before repeating.

The Fibonacci form gathers several taps into one XOR chain and feeds the result into bit zero. The Galois form turns that around. The bit leaving the top of the register re-enters along the shift path, through an XOR at each tap position. Here that means positions 0, 4, 5, and 6. Both forms walk maximal-length sequences of the same period; the state orderings differ. The Galois form's XORs are two-input and sit between neighbouring flip-flops, so no feedback wire ever crosses the whole register.

Load it in the playground and drive en low mid-run: the sequence parks and resumes without losing its place. That discipline is what makes an LFSR a well-behaved building block for scramblers and test-pattern generators.

In the waveform: watch state double (0x01, 0x02, 0x04...) until 0x80 leaves the top, then land on 0x71 as the polynomial folds back in.

In the netlist: find the XOR cells threaded between shift stages; the wire they share is the top bit on its way back in, the x^8 term.

The course builds shift registers and their feedback tricks from first principles in Shift Registers.

-- 8-bit Galois LFSR: x^8 + x^6 + x^5 + x^4 + 1, seeded with 0x01 on reset.
-- The feedback XORs sit inside the shift path: the bit leaving the top
-- re-enters at positions 0, 4, 5, and 6 as the register shifts left.
library ieee;
use ieee.std_logic_1164.all;

entity galois_lfsr is
  port (
    clk   : in  std_logic;
    rst   : in  std_logic;
    en    : in  std_logic;
    state : out std_logic_vector(7 downto 0)
  );
end entity galois_lfsr;

architecture rtl of galois_lfsr is
  signal state_r : std_logic_vector(7 downto 0);
  signal carry   : std_logic;
begin

  -- The bit shifted out of the top is the polynomial's x^8 term.
  carry <= state_r(7);

  lfsr_p : process(clk)
  begin
    if rising_edge(clk) then
      if rst = '1' then
        state_r <= x"01";
      elsif en = '1' then
        state_r(0) <= carry;                 -- x^0 tap
        state_r(1) <= state_r(0);
        state_r(2) <= state_r(1);
        state_r(3) <= state_r(2);
        state_r(4) <= state_r(3) xor carry;  -- x^4 tap
        state_r(5) <= state_r(4) xor carry;  -- x^5 tap
        state_r(6) <= state_r(5) xor carry;  -- x^6 tap
        state_r(7) <= state_r(6);
      end if;
    end if;
  end process lfsr_p;

  state <= state_r;

end architecture rtl;
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