Frequently asked questions

What is RisingEdge?

A browser-based platform for learning digital hardware design. You write real VHDL or SystemVerilog, run it through real EDA tools on our servers, and see real waveforms and synthesized netlists. Think of it as interactive practice for RTL design: lessons that teach, exercises that check your work cycle by cycle, and challenges that put a contract in front of you and dare you to meet it.

Do I need to install anything?

No. The simulators and synthesis tools (GHDL for VHDL, Icarus Verilog for SystemVerilog, Yosys for synthesis) run in sandboxed containers on our side. You need a browser. That's the point: no toolchain setup, no licenses, no "works on my machine".

Are there tool limitations I should know about?

Some. GHDL, Icarus Verilog, and Yosys are the serious open-source stack and they cover the synthesizable core of both languages well, but they're not commercial EDA. The gaps you're most likely to meet in SystemVerilog: typedef struct on ports doesn't always survive synthesis, and some RAM coding styles a commercial tool would infer as block RAM come out as flip-flops in the netlist. Simulation is usually fine; it's the netlist view where this shows. Our own content is written to stay inside what the tools do well, so if an exercise walks you into a wall, report it and we'll fix the exercise. The trade is deliberate: real tools with no licenses and nothing to install, at the cost of a few rough edges commercial tools have polished away.

Verilog or VHDL?

Both language families. Every topic is covered in VHDL and SystemVerilog, and you can switch language at any time; a small number of exercises are language-specific drills with a paired counterpart in the other language. If you know plain Verilog, SystemVerilog will feel like home: it's a superset, and our content sticks to the synthesizable core rather than exotic verification features.

Is this useful for FPGA or ASIC work?

The skills are the same ones you'd use for either: writing synthesizable RTL, reading waveforms, understanding what your code becomes after synthesis (the netlist view shows you exactly that), clock domain crossings, FSMs, pipelines. We don't target a specific FPGA family or ASIC flow; we teach the design thinking that transfers to all of them.

What does it cost?

Most of it is free: every practice challenge, the full toolchain with waveforms, netlists and Fmax timing, big simulations, the entire Fundamentals level of the curriculum, and 30 runs a day on a verified free account. One thing costs money: the course. It is a one-off payment of £99 for 12 months of the full curriculum, everything we add during your year included, with no daily run limit on any content (a generous hourly fair-use cap applies to everyone). It is not a subscription: it does not auto-renew and there is nothing to cancel. Current prices are on the pricing page; refunds are covered by the refund policy.

What exactly do I get for £99?

Twelve months of the full Learn curriculum: every topic from gates to the asynchronous FIFO, plus everything we add during your year, with no daily run limit on any of it. Practice challenges and the toolchain are free for everyone anyway.

Is it a subscription?

No. It is a one-off payment for a year of access. It does not auto-renew, there is nothing to cancel, and we do not store your card. If you want another year later, you just buy it again.

What happens when my year ends?

You keep your account, your progress, your saved runs, and everything free. Only the paid curriculum locks again.

I bought the course when it was sold as "yours forever". What now?

Nothing changes for you. Every course bought before the July 2026 pricing change keeps full access forever, exactly as promised at purchase. The 12-month model applies only to new purchases.

What happens if RisingEdge shuts down?

The honest answer: I'm building this for the long haul. But if RisingEdge ever does shut down, everyone inside a paid year gets a full refund, no questions asked. That's the commitment I can honestly make as a small company.

Can my university or team get access?

Yes. We do seat licenses for organizations: one invite link, your people claim seats, and whoever manages the license can see and manage membership (never individual progress; that stays the learner's own). Get in touch and tell us how many seats you need.

How do the challenges work?

Each challenge is a spec with teeth: a story, an interface, and a testbench that checks the contract every cycle. Some also dare you to beat a measured resource budget. The netlist viewer shows your cell and flip-flop counts, so the score is real. All challenges are free, written and maintained by us.

Do you issue certificates?

No. What you get is the ability to design hardware and a history of solved work. In this field, that tends to speak louder.

Something's broken. Where do I report it?

The Feedback button in the top navigation (when you're signed in) goes straight to us, or use the contact form for anything that needs a reply. We read everything.

Who runs this?

VANTABYTE LTD, a company registered in England & Wales. The legal details are in the terms of service.