Frequently asked questions

What is RisingEdge?

A browser-based platform for learning digital hardware design. You write real VHDL or SystemVerilog, run it through real EDA tools on our servers, and see real waveforms and synthesized netlists. Think of it as interactive practice for RTL design: lessons that teach, exercises that check your work cycle by cycle, and challenges that put a contract in front of you and dare you to meet it.

Do I need to install anything?

No. The simulators and synthesis tools (GHDL for VHDL, Icarus Verilog for SystemVerilog, Yosys for synthesis) run in sandboxed containers on our side. You need a browser. That's the point: no toolchain setup, no licenses, no "works on my machine".

Verilog or VHDL?

Both language families. Every lesson, exercise, and challenge ships in VHDL and SystemVerilog, and you can switch language at any time. If you know plain Verilog, SystemVerilog will feel like home — it's a superset, and our content sticks to the synthesizable core rather than exotic verification features.

Is this useful for FPGA or ASIC work?

The skills are the same ones you'd use for either: writing synthesizable RTL, reading waveforms, understanding what your code becomes after synthesis (the netlist view shows you exactly that), clock domain crossings, FSMs, pipelines. We don't target a specific FPGA family or ASIC flow; we teach the design thinking that transfers to all of them.

What does it cost?

There's a free tier (a slice of the curriculum and a daily allowance of runs) and a Pro subscription for everything else. Current prices are on the pricing page. Refunds and cancellation are covered by the refund policy — cancelling is self-service and you keep access until the end of what you paid for.

Can my university or team get access?

Yes — we do seat licenses for organizations: one invite link, your people claim seats, and whoever manages the license can see and manage membership (never individual progress — that stays the learner's own). Get in touch and tell us how many seats you need.

How do the challenges work?

Each challenge is a spec with teeth: a story, an interface, and a testbench that checks the contract every cycle. Some also dare you to beat a measured resource budget — the netlist viewer shows your cell and flip-flop counts, so the scoreboard is real. You can also author your own challenges: your first approved one banks you 3 days of Pro.

Do you issue certificates?

No. What you get is the ability to design hardware and a history of solved work — in this field, that tends to speak louder.

Something's broken. Where do I report it?

The Feedback button (bottom of every page) goes straight to us, or use the contact form for anything that needs a reply. We read everything.

Who runs this?

VANTABYTE LTD, a company registered in England & Wales. The legal details are in the terms of service.