In the gates lesson you wired AND, OR, XOR, and NOT one wire at a time. Since then your signals have grown into vectors Signals and Data Types, and the operators grew with them. This lesson is about what the gate operators do when you hand them a whole vector: one operator in the code, one gate per wire in the hardware.
Applied to two vectors of the same width, a bitwise operator works lane by lane. Bit 3 of the result comes from bit 3 of each operand, bit 2 from bit 2, and so on. Four independent gates from one line of code, nothing carried between lanes:
masked <= status and mask;
Work one through in binary. With status = 1011 and mask = 0110, each lane is its own AND. Lane 3 is 1 AND 0 = 0, and lane 2 is 0 AND 1 = 0. Lane 1 is 1 AND 1 = 1, and lane 0 is 1 AND 0 = 0. The result is 0010. Only lane 1 had both inputs high. The values 11 and 6 never met as numbers; bitwise operators don't read vectors as numbers at all.
not inverts every lane (not 0110 = 1001), and it combines with the others the way single-bit gates did:
ignored <= status and not mask;
Same example: ANDing 1011 with the inverted mask 1001 gives 1001, exactly the lanes of status that the mask shut out.
One rule of hygiene: keep both operands the same width.
VHDL stops with an error when the lengths differ.
Bitwise operators keep the width. Just as often you want the opposite: one bit that summarizes a whole vector. "is any alarm lane high?", "are all self-test bits passing?". That's a reduction operator: the same gate, applied across the lanes of a single vector instead of between two vectors.
any_set <= or status; -- 1 when at least one lane is high
all_set <= and status; -- 1 when every lane is high
none_set <= nor status; -- 1 when no lane is high
The operator keyword moves in front of a single vector (a VHDL-2008 form, the standard this platform uses). The inverted gates work too: nor v is "no lane high". Reduction XOR (xor v) answers "is the count of high lanes odd?".
That last one is a parity check, and it earns its keep on serial links in Parity and Framing Errors.
Read or 0010 the long way once: 0 or 0 or 1 or 0 = 1, a single OR gate tree eating the whole vector.
A reduction can also collapse an expression, not only a named signal.
Wrap the expression in parentheses first: xor (a xor b) is the parity of the lanes where two vectors differ.
Without the parentheses, the reduction grabs only the first vector and the rest of the line means something else.
VHDL has no second operator family to confuse: and, or, and not are the whole story, and the operand type decides what they mean. On vectors they work lane by lane, on single bits they are the plain gates. The truth-value role shows up when conditions enter the picture, with the comparisons in the arithmetic lesson.
The example panel on the right (Alarm Masker) is this lesson in three assignments: four sensor lanes on status, a service mask on mask. masked is the lane-by-lane AND, ignored uses not to catch the lanes the mask shut out, and alarm is the reduction OR of masked. In the waveform, find the step where status = 0010 while mask = 1101: the firing lane is masked out, so masked stays 0000 and alarm stays low. The alarm answers to enabled lanes only. Two steps later, status = 1011 against mask = 0110 reproduces this lesson's worked example: masked = 0010, ignored = 1001, and alarm high because one enabled lane survived the mask.
or v), all (and v), odd parity (xor v).sync-content --examples to generate.