Know this already? Skip to the exercise: Bus Width Adapter
Concatenation assembles a word from smaller fields: the leftmost piece occupies the most significant bits, and the field widths add together. It extends the slice-and-repack work into one expression.
A device expects two four-bit fields, hi_i first and then lo_i, so with hi_i = 0011 and lo_i = 0101 its expected byte is hexadecimal 35. A proposed implementation returns 53 instead.
Before reading the syntax, draw where each input bit belongs. Which field was placed in bits 7 through 4?
byte_o <= hi_i & lo_i;
The incorrect result reverses the two fields. A test with both fields equal would hide that mistake, which is why assembly tests want a distinct pattern in each field.
Four bits plus four bits produce eight bits, but concatenation itself is fixed wiring rather than an adder. That does not mean the physical connections have zero routing delay.
The & operator joins vectors, single bits, and literals, and the resulting width must match the assigned vector.
A four-bit unsigned value can be widened without changing its value by adding zeros on the left:
wide_o <= "0000" & lo_i;
Putting one zero on the right instead shifts each input bit to the next higher weight:
dbl_o <= "000" & lo_i & '0';
For lo_i = 0101 the output becomes 00001010. The input represents 5; shifting its bits left by one makes their weights twice as large, producing 10. The eight-bit destination also holds the maximum input 15 doubled to 30.
A fixed shift is wiring, whereas a signal-selected shift amount requires selection hardware.
Sign extension repeats the original sign bit when widening a signed representation. For the four-bit offset off_i, the sign bit is bit 3.
ext_o <= off_i(3) & off_i(3) & off_i(3) & off_i(3) & off_i;
Here the four copies are written out explicitly. Numeric resize and aggregates provide other useful forms once their types and syntax are introduced.
Suppose someone replaces the repeated sign bit with four constant ones. That implementation passes a test using 1101, which represents -3, so pick a positive offset that exposes the mistake before looking at the example.
For instance, +3 should extend from 0011 to 00000011, but constant-one padding gives 11110011, which is -13. Handling one negative value correctly does not prove the sign extension is right.
Open Wider, Three Ways in the example panel on the right. Its word_builder source performs assembly, doubling, and sign extension on separate outputs.
At the first waveform step, find byte_o = 35, dbl_o = 0A, and ext_o = 03 in hexadecimal, which mean 53, 10, and +3 respectively. The next step changes off_i to 1101; ext_o becomes FD, the eight-bit representation of -3.
A check for field order does not replace a check for signed padding. The bus-width adapter exercise asks you to apply these operations to a different interface.