You have glued bits before: the two's complement lesson handed you a sign-extension recipe as fixed syntax, on faith. This lesson is the full story behind that recipe. Concatenation builds a wider signal out of narrower pieces, and the key fact about it is what it isn't: it isn't computation. No gates, no delay, no truth table. Just wires from several bundles regrouped into one bigger bundle. The previous lesson's operators became gates; everything in this lesson becomes copper.
The concatenation operator joins vectors, single bits, and literals end to end: the same job as building a word from pieces, now in a single expression:
word <= hi & lo; -- 4 wires & 4 wires = 8 wires
Two rules govern every concatenation:
hi = 0011 and lo = 1010, the result is 00111010: hi occupies bits 7 down to 4, lo bits 3 down to 0.Pieces can be literals, which is how fixed fields and padding get into an assembled word. A 4-bit value zero-extended onto an 8-bit bus is a concatenation with a literal:
wide <= "0000" & lo; -- zero-extension: upper lanes wired low
Those four zeros are real wires held low, the same leading zeros you met when a value first landed on a too-wide bus.
Put the pad on the right instead, and something arithmetic falls out for free:
dbl <= "000" & lo & '0'; -- lo, doubled
Every bit of lo lands one position further left, and each position leftward doubles a bit's weight, so the value doubles. 0101 (5) becomes 1010 inside the result, read as 10. That is a shift left by one, and it cost nothing: no operator, no logic, just each input wire soldered one lane over. Dedicated shift operators exist for when the shift amount is a signal (they arrive in Shifting by a Signal). But for a fixed shift like this, wiring is the whole implementation.
The other direction of widening pads with copies of a signal instead of constants. The canonical case is the one you took on faith in Digital Foundations: sign extension, where every new upper bit is a copy of the sign bit.
VHDL has no replication operator; you spell out the copies with &:
ext <= off(3) & off(3) & off(3) & off(3) & off; -- four copies, spelled out
Each copy is written down by hand, and it is still pure wiring: the sign bit fanned out four times, then the value. (For numeric widening VHDL also offers a resize function that picks zero- or sign-extension from the type; it arrives with the arithmetic types in the next lesson.)
Replication isn't only for sign bits: replicating a whole vector tiles it. A 4-bit test pattern repeated four times fills a 16-bit bus.
CAUTION
Common Mistake: assembling fields in the wrong order, or with widths that don't sum to the target. Sketch the layout first (fields left to right, from the top bit down to bit 0, each with its width), then read the sketch off as one concatenation. If the widths don't add up to the target's, the sketch is wrong, not the tool.
The example panel on the right (Wider, Three Ways) does one widening job per output. word glues the two nibbles. Check the first step: hi = 0011, lo = 0101, and word reads 00110101, the two patterns side by side. dbl is the shift-by-wiring: the same 0101 (5) appears as 00001010 (10), every bit one lane left. ext sign-extends the 4-bit offset off. On the first step 0011 (+3) gains only zeros, but on the second step watch 1101 (−3) become 11111101. The high copies are the sign bit fanned out, and the value survives the move to 8 bits.
&. Sign extension is its star use.sync-content --examples to generate.