The previous lesson put constant values on wires. Gates are what compute with them: tiny circuits that read input wires and drive an output wire. And here the parallel-circuit mindset matters again: a gate is not a function call. It has no caller and no return: it recomputes its output continuously, the instant any input wire changes, whether or not anything "asked". Every gate in your design is doing this at the same time, always.
Each gate is fully described by its truth table: one row per input combination, no ambiguity, nothing left out.
NOT inverts its single input:
a | not a |
|---|---|
| 0 | 1 |
| 1 | 0 |
One line per gate, then all three side by side in one table:
a | b | a and b | a or b | a xor b |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 | 0 |
Each gate also has a schematic symbol. You will meet these shapes in every datasheet and in this platform's netlist viewer:
Two derived gates appear constantly in real hardware: NAND (AND, then NOT) and NOR (OR, then NOT). You don't need new tables for them; invert the AND and OR columns above. Their symbols are the AND and OR shapes with a small circle (the NOT "bubble") on the output:
In code, a gate is an operator inside the same concurrent assignment you met in the previous lesson:
y <= a and b;
y <= a or b;
y <= a xor b;
y <= not a;
VHDL spells the operators as words, and NAND and NOR get dedicated operators of their own: a nand b, a nor b.
Real conditions take several gates. "Sound the buzzer when the oven is hot and either door is open":
buzzer <= hot and (door_a or door_b);
Parenthesize every mix of different operators.
VHDL refuses to compile a and b or c at all: it makes you write (a and b) or c.
The parentheses are what keep the expression readable as a circuit: each pair of brackets is a gate whose output feeds the next one.
A compound expression has a truth table too, built one gate at a time. For the buzzer with inputs (hot, door_a, door_b), work the inner OR first, then AND it with hot. Row 1 0 1 gives door_a or door_b = 1, then 1 and 1 = 1: buzzer on. Row 0 1 1 gives an inner 1 but 0 and 1 = 0: doors open, oven cold, silence. Three inputs mean 2³ = 8 rows, and those 8 rows are the design's complete specification. Any two circuits with the same truth table are interchangeable, no matter how they're built. The Karnaugh maps lesson at the end of this topic builds directly on that idea.
Two identities you will use for the rest of your hardware career:
not (a and b) = (not a) or (not b) -- "not both" = "at least one missing"
not (a or b) = (not a) and (not b) -- "not either" = "both missing"
Inverting a compound condition flips AND to OR (and back) while the NOT moves onto each input. Prove the first one to yourself row by row:
a | b | a and b | not (a and b) | (not a) or (not b) |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 |
The last two columns match on every row: same truth table, interchangeable circuits. This is how you turn a requirement like "alert unless both sensors agree the guard is closed" into gates two different ways and know they're the same.
CAUTION
Common Mistake: moving the NOT inside the parentheses without flipping the operator, writing not (a and b) as (not a) and (not b). Work that wrong version out against the table: it is 1 only on the 0 0 row, while not (a and b) is 1 on three rows. They disagree on 0 1 and 1 0, so they are different circuits. The NOT moves inside only when AND flips to OR.
This lesson ships two examples. Start with Gate Gallery in the panel on the right: one design computes all six gates of a and b at once. The testbench walks the inputs through 00, 01, 10, 11 in 10 ns steps. The waveform is a truth table laid on its side. Read y_and across the four steps and you get its column: 0, 0, 0, 1. Note that all six outputs move in the same step: six gates, all computing in parallel, none waiting its turn.
Then switch the panel to De Morgan's Laws in Wires. It builds each side of both identities as a separate output (nand_direct next to nand_split, nor_direct next to nor_split) under the same input sweep. Each pair of traces is identical on every step: the proof above, in copper.
sync-content --examples to generate.