The operators so far never read a vector as a number: lanes stayed independent, wires just moved. This lesson's operators do read numbers, and that immediately raises the question from the two's complement lesson: the pattern 11110110 is 246 unsigned and is −10 signed. Same wires. Every adder and comparator you describe must know which reading you mean, and you say it through the type Signals and Data Types.
std_logic_vector has no + at all; it is deliberately just wires. Arithmetic lives on the numeric_std types unsigned and signed, which carry their reading in the type. A raw bus gets a reading by casting:
u_lt <= '1' when unsigned(a) < unsigned(b) else '0';
s_lt <= '1' when signed(a) < signed(b) else '0';
The cast costs nothing in hardware; it only tells the tools which circuit to build.
+ and - work on the numeric types directly, and integer literals mix in freely (count + 1). The trap is width: the true sum of two 8-bit numbers can reach 510, which needs nine bits.
VHDL sizes a sum to its operands: 8-bit + 8-bit is 8 bits, carry gone. So you widen the operands first with resize:
-- Widen both operands first: 255 + 255 = 510 needs nine bits
total <= resize(pallet_a, 9) + resize(pallet_b, 9);
resize is the numeric promise from the previous lesson kept: on unsigned it pads with zeros, on signed it replicates the sign bit. That is the right extension chosen by the type, the same wiring you built by hand.
WARNING
An assignment whose target is too narrow doesn't round; it drops the top of the true result. That is exactly the wrap-around overflow from the two's complement lesson, now silently built into your design. Before writing + or -, ask: how big can the true result get, and does my target have a wire for every bit of it?
Subtraction follows the same width rule, with one more edge. On unsigned, a result below zero wraps the same way a sum wraps past the top; there is no pattern for −1 among unsigned readings. When a difference can legitimately be negative, the values involved belong in signed.
Relational operators compare two values and answer with a single truth value:
| Question | Operator |
|---|---|
| equal | = |
| not equal | /= |
| less / less or equal | < <= |
| greater / greater or equal | > >= |
Equality is lane-by-lane sameness and works on any vector. The ordering operators read values as numbers, so everything above applies: the type picks the reading. The operands' widths may differ; the numeric types extend the shorter side correctly before comparing.
What do you do with the answer?
A comparison yields a boolean, which doesn't connect to a std_logic wire by itself. You route it with the conditional form you've been using as a recipe since Port Directions: over <= '1' when total > LIMIT else '0';. You first put that form to work on a comparison in Numeric Types and Constants. Still a recipe for now, explained in full in Conditional Assignment. One quirk to read past: <= is comparison inside an expression and assignment at the start of a statement. The position decides.
Comparisons inherit the two-readings problem in its sharpest form. Take a = 11110110 and b = 00000101: unsigned, that's 246 against 5, so a < b is false; signed, it's −10 against 5, and a < b is true. Same wires, opposite verdicts. Neither is wrong, until the wrong reading gets picked silently.
The type system guards you here: unsigned and signed are distinct types, and comparing one to the other refuses to compile. You must cast both sides to one reading.
This lesson ships two examples. Start with Freight Lift Guard: two pallet weights are summed into the 9-bit total and compared against a 350 kg limit. In the waveform, find the last step (255 + 255) and read total: 510, a value no 8-bit signal could hold. Without the widening it would have wrapped to 254 and read as a safe load. Then watch over across the two middle steps: low at exactly 350, high at 351, because > means strictly greater. And empty is the table's equality row at work: high only on the first step, when the lift carries nothing and total reads zero.
Then switch to Same Wires, Two Verdicts: one pair of raw buses feeds two comparators, one casting both sides unsigned, one signed. The readings agree on small positive patterns, and split the moment a top bit goes high. At a = F6, b = 05, u_lt says no (246 < 5 fails) while s_lt says yes (−10 < 5 holds). Two verdicts from identical wires, differing only in the reading you asked for.
In this lesson a single + or > bought you a whole adder or comparator, built by the tools. What those circuits look like inside (half and full adders, carry chains, an ALU you assemble yourself) is where arithmetic continues, in Arithmetic Circuits.
unsigned or signed.resize the operands first. Keep possibly-negative differences in signed.'1' when ... else '0'. And never let the two readings mix in one comparison.sync-content --examples to generate.