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Practice

Self-contained HDL challenges, free for everyone. Pick one and solve it right in your browser.

Language
Difficulty

Chocolate Box Splitter

intermediate · ~25 min

A serial restoring divider computes an 8-bit quotient and remainder, one bit per cycle, with start, busy, and done control and a divide-by-zero flag.

arithmeticsequentialshift-register
0 solves
VHDLSV

Trail Camera SD Wake

advanced · ~40 min

Walk a fresh SD card through its SPI-mode wake ritual and refuse to say ready until the card is

state-machinesspisd-card
0 solves
VHDLSV

Pressure Rig DAC Staircase

beginner · ~15 min

Walk a parallel DAC from zero to full scale with the datasheet's setup and hold guarded around every write strobe

sequentialcounteradc-dac
0 solves
VHDLSV

Plant PHY Register

advanced · ~40 min

Read a PHY register over MDIO and let go of the wire for the turnaround the protocol promises

state-machinesethernettristate
0 solves
VHDLSV

Forklift CAN Arbitration

advanced · ~40 min

Send a CAN arbitration field, listen to every bit you drive, and go silent the moment a lower identifier wins

state-machinescan
0 solves
VHDLSV

Coating Booth Recipe Core

advanced · ~40 min

Build an eight-instruction accumulator CPU that alternates fetch and execute every two clocks and runs legacy 32-byte programs opcode for opcode.

state-machinesmemoryalu
0 solves
VHDLSV

Service LCD Startup

intermediate · ~25 min

Walk a four-bit character display through its wake ritual before feeding it characters as timed nibble pairs

state-machinescounterdisplay
0 solves0/1 passed
VHDLSV

Dock RMII Receiver

advanced · ~40 min

Find the real start of an Ethernet frame on two-bit RMII pins before packing anything into bytes

state-machinesshift-registerethernet
0 solves
VHDLSV

Workshop PS2 Keyboard

advanced · ~40 min

Receive PS/2 scan codes through two-flop synchronizers and drop every frame with a bad start, parity, or stop bit

state-machinessynchronizerps2
0 solves
VHDLSV

Silo RS485 Burst

advanced · ~40 min

Send a three-byte UART burst through a half-duplex transceiver whose driver enable leads the first bit and outlives the last stop bit

state-machinesuartrs485
0 solves
VHDLSV

Packing Camera Capture

advanced · ~40 min

Assemble RGB565 pixels from an 8-bit camera bus and recover the byte pairing at every line

state-machinesregistercamera
0 solves
VHDLSV

Market Sign LED Chain

intermediate · ~25 min

Drive a two-lamp one-wire smart LED chain with exact pulse widths and a latch gap the chips can trust

state-machinescounterled-strip
0 solves
VHDLSV

Codec I2S Receiver

advanced · ~40 min

Capture 16-bit stereo words from an I2S codec, honoring the one-bit delay after each word-select change so no sample loses its top bit

state-machinesshift-registeri2s
0 solves
VHDLSV

Archive Flash Burst

advanced · ~40 min

Issue a SPI fast-read with its dummy phase intact and stream four bytes back under one chip select

state-machinesspi
0 solves
VHDLSV

Pump Leg Dead Time

advanced · ~40 min

Build a complementary PWM gate drive that inserts an exact two-clock dead time at every hand-off so the two switches never conduct together.

state-machinescounter
0 solves
VHDLSV

Kiln ADC Pair Capture

intermediate · ~25 min

Keep a dual-channel ADC's temperature and pressure samples paired, and refuse to publish when the channel tags fall out of step

state-machinesregisteradc-dac
0 solves
VHDLSV

Lane Rack Button

beginner · ~15 min

Build a button debouncer with a two-flop synchronizer, an 8-sample stability filter, and one-cycle pressed and released pulses.

sequentialcountersynchronizer
0 solves
VHDLSV

Synth Cutoff Dial

beginner · ~15 min

Build an 8-bit PWM DAC that samples its level only at period boundaries, so the pulse in flight never changes width mid-period.

sequentialcounteradc-dac
0 solves
VHDLSV

Loft Clock Wire

beginner · ~15 min

Build a UART transmitter that sends each byte LSB first with start and stop bits, every bit exactly 8 clocks wide.

state-machinesuart
0 solves
VHDLSV

Hive Scale Sampler

intermediate · ~25 min

Build a SPI master that pulls 12-bit samples from a serial ADC, capturing each bit on the correct clock edge and skipping the null bits.

state-machinesspiadc-dac
0 solves
VHDLSV

Stirrer Sign-Off

intermediate · ~25 min

Write a full acceptance testbench from a stir-and-rest controller spec, passing the good unit and catching two known-bad revisions.

verificationstate-machines
0 solves
VHDLSV
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