Majority Voter, Two Ways

Safety-critical systems often triplicate a sensor and let the copies vote: the output follows the majority: '1' whenever at least two of the three inputs are '1'. The template already contains a working implementation built minterm-by-minterm from the truth table. Your job is to add a second implementation of the same function, living behind the same interface. Write the K-map-minimized form: three two-input AND terms OR'd together (the minimization technique is from Digital Foundations).

• VHDL: add a second architecture named minimized to the existing majority_voter entity. Leave the given minterms architecture untouched.
• SystemVerilog: add a sibling module named majority_voter_minimized with the identical port list. Leave the given majority_voter module untouched.

The testbench instantiates the given implementation and yours side by side and drives all eight input combinations; both must produce the majority on every row.

Interface (both implementations)

Behavior

• vote is '1' when two or three inputs are '1', and '0' otherwise
• Both implementations are checked on every one of the 8 input combinations

Constraints

• Don't modify the given implementation; the testbench checks it too.
• Expect the first run to fail before your unit exists: VHDL stops with cannot find architecture "minimized" of entity "majority_voter"; SystemVerilog with Unknown module type: majority_voter_minimized. Write the unit and the error disappears.