Anatomy of a Component

A remote sensor holds its status line high while healthy. Your monitor must pass that level to another component and raise an alarm while the line is low. Before writing syntax, name the boundary: one incoming signal, two outgoing signals, and no stored history.

An HDL component packages an interface with the logic behind it. Its ports are named connections, not necessarily physical package pins: many connect components inside the same FPGA.

Write one complete component

In earlier exercises, the file around your assignments was supplied. Here is the complete line_monitor from the example panel:

library ieee;
use ieee.std_logic_1164.all;

entity line_monitor is
  port (
    line_i  : in  std_logic;
    line_o  : out std_logic;
    alarm_o : out std_logic
  );
end entity line_monitor;

architecture rtl of line_monitor is
begin
  line_o  <= line_i;
  alarm_o <= not line_i;
end architecture rtl;

Find the line that names the component, the three port declarations, and the two logic assignments. Each port declaration answers three questions:

Part	Meaning here
Name	`line_i`, `line_o`, or `alarm_o`; connections elsewhere use these names
Direction	The surrounding design supplies the input; this component drives the outputs
Type	Each port carries one bit, with additional simulation values for unknown or disconnected signals

The _i and _o suffixes help humans read direction. They are a course convention, not language keywords.

The entity declares the interface. The architecture describes its implementation; of line_monitor connects the two by name. rtl is this architecture's name, not a special command.

std_logic comes from the IEEE package imported by the first two lines. Keep that preamble when using it. Later, arithmetic with unsigned and signed also needs ieee.numeric_std.all.

Connections keep working

These assignments are concurrent: both remain active, and neither waits for the other to finish. Reversing their order does not reverse the circuit. For a binary input, the outputs follow this rule:

`line_i`	`line_o`	`alarm_o`
0	0	1
1	1	0

The pass-through is a connection and the alarm path includes an inverter. There is no clock or remembered fault here. The simulation models no physical propagation delay, but real wires and gates take time to settle.

One source can feed two destinations

Does the alarm create a driver conflict?

Question 1 of 1

For ordinary internal RTL, give each signal one owning driver and as many readers as needed. Deliberately shared, resolved wires follow a different ownership rule in Port Directions.

Check a changed requirement

In the read-only example waveform, find the first low interval and the recovery that follows it. Does the alarm remain high after recovery? Now suppose a maintenance display must remember that a fault happened, even after the sensor recovers. Explain why this component cannot satisfy that new requirement unchanged. You would need storage; renaming an output would not add it.

The next exercise is where you write a complete interface yourself. One Interface, Many Implementations then separates a component's public contract from its implementation.

Key Takeaways

Ports state what crosses a component boundary: name, direction, and type.
Concurrent assignments describe continuously active logic, not a sequence of software steps.
Reading one input in several places is fan-out, not a multiple-driver conflict.

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