Machine Status Panel

A machine controller exposes two status lines, RUN and FAULT, and the wiring plan calls for a status panel. Each line lights its own lamp, and the fault line also sounds a horn. Nothing is computed here. The point of this exercise is that, for the first time, you write the component's boundary. The template provides only the empty shells, with the entire port list missing.

Declare all five ports from the table below, then wire each output to its input.

Interface

Declarations: VHDL, all ports std_logic; SystemVerilog, all ports logic.

Behavior

• panel_run follows run at all times
• panel_fault follows fault at all times
• horn also follows fault: one input feeding two destinations
• The testbench steps through the input combinations and checks all three outputs at every step

Constraints

• Three concurrent assignments are all you need; no other constructs
• Expect the first run to fail before you've declared the ports: the testbench can't connect to a component that has none. VHDL stops with signal "run" is not an interface name; SystemVerilog with port ``run'' is not a port of dut, one such line per missing port. Declare the ports and the errors disappear.