Pump Leg Dead Time

Merefield Grain Depot fitted a new motor drive on the drainage pump in its intake pit. The drive switches one phase leg with two power transistors.

One transistor is high and one is low. Only one may ever be on at a time.

The shipped logic got that wrong. Each time the PWM changed sides, both gate signals stayed on together for one clock.

The transistors shorted the DC bus, and the first power stage burned. Black soot marked the cabinet door.

The pump stood still. Rain filled the pit, and the depot could not take the grain trailer waiting outside.

Your task: build the dead-time stage for this leg. When conduction changes sides, hold both gates off for exactly two clocks, then let the new side turn on.

Interface

Behavior

• While enable is high, a free-running PWM counter advances from 0 through 31, then wraps to 0
• The PWM period is always 32 clocks
• duty is captured only when the counter wraps to 0 and when the drive is re-enabled
• Changes to duty during a period do not affect that running period
• Captured duty values above 32 count as 32
• For a captured duty of d, the high side ideally owns counter values 0 through d - 1
• The low side ideally owns counter values d through 31
• A gate turns low immediately when its ideal window ends
• When ideal ownership moves to a side, its gate remains low for that counter cycle and the following counter cycle
• If that side still owns the third consecutive counter cycle, its gate turns high at the edge starting that cycle
• If an ideal window ends during its two-clock delay, that gate does not turn on during that window
• A handoff is a turn-off followed by the opposite gate actually turning on. At every handoff, both gates are low for exactly two clocks first
• With duty 1 or 31 the incoming side's window expires inside its own delay, so that gate never rises and the low stretch runs longer. That is not a handoff
• gate_hi and gate_lo must never be high together
• With duty 0, the low side owns the whole period
• With duty 32, the high side owns the whole period
• After its initial two-clock delay, a whole-period owner stays on continuously across period boundaries without a spurious gap
• enable low forces both gates low at the next rising edge, regardless of the current side or dead-time state
• Disabling the drive resets the period counter to 0
• On re-enable, a fresh period starts at counter 0 and captures the current duty
• The first gate turn-on after re-enable still waits the full two-clock delay
• rst high at a rising edge clears both gates, resets the counter to 0, and clears the captured duty to 0

What the bench checks

• The testbench compares both gate outputs cycle by cycle against a reference model
• Any cycle with both gates high fails immediately
• The testbench checks exactly two both-low clocks at every side handoff
• It changes duty during periods and checks that new values apply only at boundaries
• It checks duties 0, 1, 31, and 32, plus values above 32 that must clamp to 32
• It disables the drive while each side is conducting, then re-enables and checks the complete two-clock turn-on delay
• It asserts reset at a period boundary and inside a dead-time gap

Constraints

Do not add ports.