Archive Flash Burst

At dawn, the ferry Alder Rose loads its voyage recorder settings from a small SPI flash chip before leaving Ramsgate.

A replacement reader board came back from repair with a clear fault. On a fan-fold hex dump, every page began with FF and lost its last real byte.

The flash chip's fast-read command needs eight dummy clocks between the address and the first data bit. The repaired board had saved that dummy byte as data.

Your task: build a reader that treats the chip's phases as law. Send the command, address, and dummy clocks, then collect four real data bytes.

Interface

Behavior

• Only an idle reader accepts start_i, and the read it triggers begins one clock later
• The reader copies addr_i at the moment of acceptance
• A read in progress works from that copy, so later addr_i changes cannot reach it
• start_i pulses that arrive while busy_o is high are dropped without effect
• On the next clock, busy_o rises and cs_n_o falls to begin the transaction
• While idle, cs_n_o is high, sclk_o is low, and mosi_o is low
• Each read uses one continuous transaction under a single cs_n_o low period
• cs_n_o falls exactly one system clock before the first rising sclk_o edge
• cs_n_o stays low through the last data bit
• SPI mode 0 is used, with exactly two system clocks for every SPI bit
• sclk_o is low during a bit's first system clock and high during its second
• mosi_o is set during the low phase and remains stable before the rising sclk_o edge
• miso_i is sampled on each rising sclk_o edge
• The first phase sends the fast-read opcode 0x0B, most significant bit first
• The next phase sends all 24 captured address bits, most significant bit first
• The next phase sends eight dummy bits, all driven low on mosi_o
• After the dummy phase, 32 more sclk_o cycles read four data bytes from miso_i
• Data is received most significant bit first within each byte
• mosi_o remains low throughout the complete data phase
• When each byte completes, data_o updates and valid_o pulses for one system clock
• data_o holds its latest completed byte between valid_o pulses
• After the fourth valid_o pulse, sclk_o falls on the next clock and done_o pulses for that clock
• busy_o remains high and cs_n_o remains low during the done_o pulse
• One system clock after the final sclk_o fall, cs_n_o rises and busy_o falls
• The unit is idle when cs_n_o returns high and busy_o falls
• rst_i high at any rising edge aborts the read and clears all transaction progress
• Reset forces cs_n_o high and forces sclk_o, mosi_o, busy_o, valid_o, and done_o low
• No read aborted by reset resumes afterward

What the bench checks

• A flash model decodes the opcode and address off mosi_o at each rising sclk_o edge and serves four bytes derived from the address it heard
• The dummy phase is the trap: a valid_o pulse before transaction clock 95 is flagged as the dummy byte landing in the data
• Each read must fit one chip-select window: 145 clocks low with exactly 72 rising sclk_o edges inside it
• cs_n_o must fall one clock before the first sclk_o rise and rise one clock after the last fall
• mosi_o may never change on a clock where sclk_o rose or stayed high
• addr_i switches to a decoy one clock after acceptance, and extra start_i pulses land mid-dummy, mid-data, and on the done clock
• It asserts reset in the command, dummy, and data phases and expects idle pins at once with no aborted read resuming

Constraints

TIMING: everything is synchronous to clk_i; inputs are sampled on rising edges, and all outputs are registered.

SCOPE: this models the four logic pins of a mode-0 SPI link and the fast-read phase order. Electrical drive, real flash latencies, and other flash commands are out of scope.

Do not add ports.