Archive Flash Burst

At dawn, the ferry Alder Rose loads its voyage recorder settings from a small SPI flash chip before leaving Ramsgate.

A replacement reader board came back from repair with a clear fault. On a fan-fold hex dump, every page began with FF and lost its last real byte.

The flash chip's fast-read command needs eight dummy clocks between the address and the first data bit. The repaired board had saved that dummy byte as data.

Your task: build a reader that treats the chip's phases as law. Send the command, address, and dummy clocks, then collect four real data bytes.

Interface

Behavior

• Only an idle reader accepts start, and the read it triggers begins one clock later
• The reader copies addr at the moment of acceptance
• A read in progress works from that copy, so later addr changes cannot reach it
• start pulses that arrive while busy is high are dropped without effect
• On the next clock, busy rises and cs_n falls to begin the transaction
• While idle, cs_n is high, sclk is low, and mosi is low
• Each read uses one continuous transaction under a single cs_n low period
• cs_n falls exactly one system clock before the first rising sclk edge
• cs_n stays low through the last data bit
• SPI mode 0 is used, with exactly two system clocks for every SPI bit
• sclk is low during a bit's first system clock and high during its second
• mosi is set during the low phase and remains stable before the rising sclk edge
• miso is sampled on each rising sclk edge
• The first phase sends the fast-read opcode 0x0B, most significant bit first
• The next phase sends all 24 captured address bits, most significant bit first
• The next phase sends eight dummy bits, all driven low on mosi
• After the dummy phase, 32 more sclk cycles read four data bytes from miso
• Data is received most significant bit first within each byte
• mosi remains low throughout the complete data phase
• When each byte completes, data updates and valid pulses for one system clock
• data holds its latest completed byte between valid pulses
• After the fourth valid pulse, sclk falls on the next clock and done pulses for that clock
• busy remains high and cs_n remains low during the done pulse
• One system clock after the final sclk fall, cs_n rises and busy falls
• The unit is idle when cs_n returns high and busy falls
• rst high at any rising edge aborts the read and clears all transaction progress
• Reset forces cs_n high and forces sclk, mosi, busy, valid, and done low
• No read aborted by reset resumes afterward

What the bench checks

• A flash model decodes the opcode and address off mosi at each rising sclk edge and serves four bytes derived from the address it heard
• The dummy phase is the trap: a valid pulse before transaction clock 95 is flagged as the dummy byte landing in the data
• Each read must fit one chip-select window: 145 clocks low with exactly 72 rising sclk edges inside it
• cs_n must fall one clock before the first sclk rise and rise one clock after the last fall
• mosi may never change on a clock where sclk rose or stayed high
• addr switches to a decoy one clock after acceptance, and extra start pulses land mid-dummy, mid-data, and on the done clock
• It asserts reset in the command, dummy, and data phases and expects idle pins at once with no aborted read resuming

Constraints

Do not add ports.