Kiln ADC Pair Capture

At Redbank Pottery, a kiln monitor reads one dual-channel ADC chip. Channel A is the kiln temperature probe. Channel B is the burner gas pressure sensor.

After a lightning storm, the converter clock line failed for a moment. The channels fell out of step.

On the paper trend chart, a pressure code landed in the red temperature trace.

The controller believed the kiln was cold, and the burner roared far too hard. Your task: build a capture stage that keeps each A and B sample paired. It must refuse to publish when the channel tags misbehave.

Interface

Behavior

• The ADC changes adc_data_i, chan_i, and overrange_i after falling adc_clk_i edges
• The capture stage samples all inputs only on rising adc_clk_i edges
• One sample arrives on every rising edge
• A healthy stream strictly alternates channel A, channel B, channel A, channel B
• A pair is one usable channel A sample followed directly by one usable channel B sample
• Capture starts by expecting a channel A sample
• A usable channel A sample becomes the first sample of a pair
• The next sample must be a usable channel B sample to complete that pair
• On the rising edge after the clean B sample is captured, sample_a_o and sample_b_o update together
• pair_valid_o pulses for that same rising edge and remains low at other times
• sample_a_o and sample_b_o hold their values between published pairs
• A channel B sample when A is expected is a tag violation
• A channel A sample when B is expected is a tag violation
• A tag violation sets fault_o high on that rising edge
• fault_o stays high until reset
• A tag violation discards the pair in progress, which is never published
• After a violation, capture waits for the next usable channel A sample
• If the violating sample is a usable channel A sample, that sample starts the new pair
• Publishing resumes after the next clean A-then-B pair, while fault_o remains high
• A sample with overrange_i high is unusable and discards the pair in progress
• An over-range sample publishes nothing and does not change fault_o
• An over-range sample is not treated as a tag violation
• After an over-range sample, capture waits for the next usable channel A sample
• rst_i high at a rising edge clears all outputs and discards all capture progress
• After reset, sample_a_o, sample_b_o, pair_valid_o, and fault_o are zero
• After reset, capture expects a channel A sample first
• All outputs are registers

What the bench checks

• The testbench changes ADC inputs after falling edges and checks sampling only on rising edges
• It sends known 12-bit patterns and checks that channel A and B samples remain correctly paired
• It checks that outputs update together one rising edge after the clean B sample, never on the B edge itself
• It sends B when A is expected and checks that the partial pair is discarded
• It sends A when B is expected and checks that this A starts a fresh pair
• It checks that clean pairs can publish after re-anchoring while fault_o stays high
• It marks A and B samples as over-range and checks that the doomed pair never publishes and fault_o never moves
• It asserts reset during capture and checks that all outputs and internal progress clear

Constraints

TIMING: everything is synchronous to adc_clk_i; inputs are sampled only on rising edges, and all outputs are registered.

SCOPE: this models the digital capture contract on the ADC clock only; board-level setup/hold, pin constraints, and the analog front end are out of scope.

Do not add ports.