Practice
Kiln ADC Pair Capture
At Redbank Pottery, a kiln monitor reads one dual-channel ADC chip. Channel A is the kiln temperature probe. Channel B is the burner gas pressure sensor.
After a lightning storm, the converter clock line failed for a moment. The channels fell out of step.
On the paper trend chart, a pressure code landed in the red temperature trace.
The controller believed the kiln was cold, and the burner roared far too hard. Your task: build a capture stage that keeps each A and B sample paired. It must refuse to publish when the channel tags misbehave.
Interface
| Port | Direction | Type | Description |
|---|---|---|---|
adc_clk | in | 1 bit | ADC data clock and the only DUT clock |
rst | in | 1 bit | Synchronous reset (active high) |
adc_data | in | 12-bit vector | Sample from the converter |
chan | in | 1 bit | Channel tag: 0 for A temperature, 1 for B pressure |
overrange | in | 1 bit | Sample is beyond the converter's full-scale range |
sample_a | out | 12-bit vector | Last published channel A sample, held |
sample_b | out | 12-bit vector | Last published channel B sample, held |
pair_valid | out | 1 bit | Pair published (one-clock pulse) |
fault | out | 1 bit | Sticky channel-tag fault |
Behavior
- The ADC changes
adc_data,chan, andoverrangeafter fallingadc_clkedges - The capture stage samples all inputs only on rising
adc_clkedges - One sample arrives on every rising edge
- A healthy stream strictly alternates channel A, channel B, channel A, channel B
- A pair is one usable channel A sample followed directly by one usable channel B sample
- Capture starts by expecting a channel A sample
- A usable channel A sample becomes the first sample of a pair
- The next sample must be a usable channel B sample to complete that pair
- On the rising edge after the clean B sample is captured,
sample_aandsample_bupdate together pair_validpulses for that same rising edge and remains low at other timessample_aandsample_bhold their values between published pairs- A channel B sample when A is expected is a tag violation
- A channel A sample when B is expected is a tag violation
- A tag violation sets
faulthigh on that rising edge faultstays high until reset- A tag violation discards the pair in progress, which is never published
- After a violation, capture waits for the next usable channel A sample
- If the violating sample is a usable channel A sample, that sample starts the new pair
- Publishing resumes after the next clean A-then-B pair, while
faultremains high - A sample with
overrangehigh is unusable and discards the pair in progress - An over-range sample publishes nothing and does not change
fault - An over-range sample is not treated as a tag violation
- After an over-range sample, capture waits for the next usable channel A sample
rsthigh at a rising edge clears all outputs and discards all capture progress- After reset,
sample_a,sample_b,pair_valid, andfaultare zero - After reset, capture expects a channel A sample first
- All outputs are registers
What the bench checks
- The testbench changes ADC inputs after falling edges and checks sampling only on rising edges
- It sends known 12-bit patterns and checks that channel A and B samples remain correctly paired
- It checks that outputs update together one rising edge after the clean B sample, never on the B edge itself
- It sends B when A is expected and checks that the partial pair is discarded
- It sends A when B is expected and checks that this A starts a fresh pair
- It checks that clean pairs can publish after re-anchoring while
faultstays high - It marks A and B samples as over-range and checks that the doomed pair never publishes and
faultnever moves - It asserts reset during capture and checks that all outputs and internal progress clear
Constraints
everything is synchronous to adc_clk; inputs are sampled only on rising edges, and all outputs are registered.
this models the digital capture contract on the ADC clock only; board-level setup/hold, pin constraints, and the analog front end are out of scope.
Do not add ports.
Click Run to execute your code. Output will appear here.