Freight Lift Link

The freight lift in an old printing house is getting new electronics, but not new wiring. One twisted pair (a two-wire signal cable) runs from the cab panel down the shaft. Pulling fresh cable through 60 years of conduit is not in the budget. Over that pair the panel sends command frames, 1 bit per clock, synchronous to the clock the controller already distributes. A frame is a start bit, 4 data bits, and a stop bit. The line idles high.

The maintenance log records two recurring problems with the receiver you are replacing. When electrical noise corrupted a frame, the receiver flagged an error but then treated the next low sample from that damaged frame as a new start bit. It stayed misaligned until someone power-cycled the cab. It also needed an idle gap to re-arm. When the operator keyed commands quickly, the second frame was quietly dropped, and goods went to the wrong floor.

Your task: build the receiver. Watch rx, recover each frame's 4 data bits, and pulse valid for a good frame or ferr for a broken one.

Interface

Behavior

• A frame is 6 samples: start bit 0, four data bits LSB first (first data sample is data(0)), stop bit 1
• rx is sampled at every rising clock edge
• While hunting, a sampled 0 is a start bit; the next four samples are data, and the sample after those is the stop bit
• Stop bit sampled 1: valid is high for exactly one cycle (the cycle after the stop sample) and data presents the frame's payload
• data holds its value until the next good frame
• Stop bit sampled 0: framing error; ferr is high for exactly one cycle instead, valid stays low, and data keeps its previous value
• After a framing error the receiver ignores the line until it samples a 1; only after that may a sampled 0 start a new frame
• After a good frame there is no idle requirement: the sample immediately after the stop bit may be the next start bit
• A line held low produces exactly one framing error, then silence until the line returns high
• valid and ferr are never high in the same cycle
• rst = 1 at a clock edge returns the receiver to hunting and clears data, valid, and ferr

What the bench checks

• The testbench checks valid and ferr on every cycle
• Normal and back-to-back frames must capture four data bits least-significant first and pulse valid for one cycle
• A bad stop bit must pulse only ferr and preserve the last good data word
• A low line after that error must not start another frame until the line returns high
• A sustained break must raise exactly one framing error, then recover for a clean frame after release
• Reset mid-frame must abandon the partial word, clear the saved data, and allow a new frame afterward

Constraints

Do not add ports.