Practice

Bottling Line Eject Delay

Line 2 caps six hundred bottles a minute. A camera watches each cap go on, and when one goes on crooked it raises flag_i for one clock cycle. The conveyor then carries the bad bottle three positions downstream to an air jet that blows it off the line. The conveyor moves exactly one position per clock cycle.

The block that shipped gets the delay wrong: one cycle instead of three. The jet fires while the bad bottle is still two positions away. It blasts a good bottle off the line, and the crooked cap sails on into a shipped case.

Your task: fix the shipped block in place so that eject_o copies flag_i with a delay of exactly 3 cycles. Whatever flag_i was 3 cycles ago is what eject_o must be now. The three delay registers are already declared and named in the template. The wiring between them is the bug; don't start over.

Interface

PortDirectionTypeDescription
clk_iin1 bitClock, one conveyor position per cycle
rst_iin1 bitSynchronous reset (active high)
flag_iin1 bitReject flag from the camera, 1 cycle wide
eject_oout1 bitEjector fire command (registered)

Behavior

DELAY: eject_o reproduces flag_i delayed by exactly three clock cycles. eject_o during any cycle equals flag_i three cycles earlier.

  • Pulse shapes are preserved exactly: single-cycle flags come out single-cycle, back-to-back patterns come out unchanged
  • rst_i = 1 at a clock edge clears eject_o and every delay stage; flags already in flight are discarded and must never emerge after the reset
  • After reset is released, eject_o stays 0 until the first post-reset flag has had its three cycles

One trace tells the whole story: a flag in cycle 1 fires the jet in cycle 4, three positions later.

cycle : 0 1 2 3 4 5
flag_i  : 0 1 0 0 0 0
eject_o : 0 0 0 0 1 0

What the bench checks

  • The testbench checks eject_o on every cycle
  • A single flag_i pulse must produce one eject_o pulse exactly three cycles later
  • Two flags with a one-cycle gap must emerge with the same gap, without extra pulses
  • Four consecutive flag cycles must become four consecutive eject cycles after the fixed delay
  • Reset while flags are in flight must flush them, prevent ghost ejects, and leave the delay ready for a new flag

Constraints

TIMING: everything is synchronous to clk_i and eject_o is registered.

SCOPE: this models the three-cycle delay between the camera's flag and the air jet. The camera, the conveyor, and the jet hardware are out of scope.

The template contains the shipped implementation: fix it in place rather than starting over. The three delay stages are already declared and the structure is right.

Do not add ports.

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