Drive Fault Register

Four fault detectors watch the 200-kilowatt drive on the quarry's main conveyor: overcurrent, overtemperature, DC bus undervoltage, encoder loss. Each raises its line for a clock cycle when it fires, sometimes longer. The plant controller (a PLC) polls a status register and acknowledges faults by writing ones back to the bits it has dealt with.

The old register cleared the whole word whenever the PLC acknowledged anything. One day a technician acknowledged a stale overtemperature bit at the same moment the overcurrent detector fired. The fresh fault vanished. The drive restarted into a shorted phase, and the motor spent a month at the repair shop.

Your task: build the replacement exactly as specified below. Each detector sets its own bit, and the bit stays set until acknowledged. A clear touches only the bits it names. When a clear and a fresh fault hit the same bit at the same edge, the fault wins. A fault register that can lose a fault is worse than no fault register at all.

Interface

Behavior

• fault_i(i) = 1 at a clock edge sets status_o(i) at that edge; the bit stays 1 after the fault line drops
• clear_i(i) = 1 at a clock edge clears status_o(i), unless fault_i(i) is also 1 at the same edge: set beats clear, and the bit stays 1
• Bits are independent: clearing one bit never disturbs the others, and clearing a bit that is already 0 does nothing
• A fault line held high across several edges keeps setting its bit; that is harmless
• rst_i = 1 at a clock edge clears all four bits, even if fault lines are high at that edge

What the bench checks

• The testbench checks all four bits of status_o after every event
• One-cycle faults must stick, and multiple fault bits arriving together must join the saved status
• Clearing one bit must leave other set bits alone, while clearing an already-clear bit must do nothing
• Simultaneous set and clear operations on different bits must act independently
• When the same bit is set and cleared together, set must win
• Reset must beat all four active fault inputs, which must set the register again if they remain high afterward

Constraints

TIMING: everything is synchronous to clk_i and status_o is registered.

SCOPE: this models the status register between the detectors and the PLC. The four detectors, the PLC's polling bus, and the drive itself are out of scope.

PRIORITY: set beats clear, handled per bit. No cycle may exist where an arriving fault is lost.

Do not add ports.