Drop-In U9

U9 is a small custom interface chip on the controller board inside fuel pump number 4. The pump head, the unit customers actually use, raises req with a byte on d. U9 answers on ack while presenting the byte to the main board on q. The chip vendor announced the final production run years ago, and nobody stocked up. Now U9s are dying at pumps across the whole chain of stations. The service company wants the function moved into the spare programmable logic chip 2 cm away on the same board.

There is no datasheet, and the archive sites have nothing. What you have instead is better. A field technician clipped a logic analyzer onto a healthy pump: a tool that records every digital signal, cycle by cycle. It captured U9 doing its job. The capture is 20 cycles long: 3 transactions and 1 power-on reset. Every rule the chip follows is somewhere in it.

Your task: write a replica that behaves identically, cycle for cycle.

Interface

Behavior

The capture below is the specification. One column per clock cycle, read like a logic analyzer trace: a column shows each signal's level while that cycle is in flight. The rising edge that ends column N is where the part samples column N's inputs. The response then lands in column N+1 (req goes high in column 3, ack answers in column 4). d and q are hex.

cycle |  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19
------+------------------------------------------------------------
rst   |  1  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
req   |  0  0  0  1  1  1  1  0  0  1  1  0  1  1  1  0  0  0  0  0
d     | 00 00 3C 3C 3C 91 91 91 91 5A 5A 5A A7 A7 22 22 22 00 00 00
ack   |  0  0  0  0  1  1  1  1  0  0  1  1  0  1  1  1  0  0  0  0
q     | 00 00 00 00 3C 3C 3C 3C 3C 3C 5A 5A 5A A7 A7 A7 A7 A7 A7 A7

• rst is synchronous
• Whenever rst is 1 at a rising edge, the part returns to the state of cycles 0 and 1 (ack low, q at 00), whatever else is happening

What the bench checks

• The testbench replays this capture cycle for cycle and checks ack and q on every cycle
• It then runs the same transaction shapes again with different bytes, longer phases, and heavier noise on d mid-handshake; everything it enforces is exhibited somewhere in the capture
• The bench asserts rst once more in the middle of a handshake

Constraints

Match the capture exactly, including the cycles nobody would think to ask about. Do not add ports. Do not try to special-case the literal byte values in the trace: the second run uses different ones.