Practice
Feeder Power Path
The substation monitor samples voltage and current on all three phases of feeder 7 and computes instantaneous power, p = va*ia + vb*ib + vc*ic, once per clock. The block in your editor has done that job for four years at 25 MHz without a complaint. Then the protection team asked for faster disturbance capture and the platform clock moved to 100 MHz. The timing report turned red: three multiplies and two adds no longer fit in a single cycle.
The catch is downstream. The disturbance recorder lines p up against the raw sample stream, and it assumes p arrives exactly two cycles after the samples it came from. That number is hard-coded.
Your task: keep computing p = va*ia + vb*ib + vc*ic, one result per clock. Deliver each result exactly 2 cycles after its samples. Split the math into two pipeline stages, so the longest path between registers gets shorter. The 2-cycle contract must hold exactly.
Interface
| Port | Direction | Type | Description |
|---|---|---|---|
clk | in | 1 bit | Clock |
rst | in | 1 bit | Synchronous reset (active high) |
va | in | 8-bit vector | Phase A voltage sample (unsigned) |
ia | in | 8-bit vector | Phase A current sample (unsigned) |
vb | in | 8-bit vector | Phase B voltage sample (unsigned) |
ib | in | 8-bit vector | Phase B current sample (unsigned) |
vc | in | 8-bit vector | Phase C voltage sample (unsigned) |
ic | in | 8-bit vector | Phase C current sample (unsigned) |
p | out | 18-bit vector | va*ia + vb*ib + vc*ic (registered) |
Behavior
exactly two cycles. A sample set on the inputs during one cycle shows on p two cycles later, not one, not three. The data passes two rising edges: the one that captures it, then the output register's.
- Throughput is one result per cycle: a new sample set arrives at every edge and every result must appear, in order, with no gaps
rst = 1at a clock edge clears every pipeline stage, and results already in flight are discarded- After a reset edge,
pis 0 during the following cycle and the one after it - All arithmetic is unsigned; the 18-bit output cannot overflow (maximum value is 3 * 255 * 255 = 195075)
What the bench checks
- The testbench checks
pon every cycle, including the two warm-up cycles after each reset - A reference pipeline requires each three-phase sum to appear exactly two clocks after its inputs
- A full-rate stream covers zero, maximum, mixed, asymmetric, and equal-sum sample sets with a new set every clock
- Reset mid-stream must clear the output, discard the sample in flight, and leave both stages clean during refill
- After refill, directed products must resume at the same exact latency without dropped or duplicated results
Constraints
everything is synchronous to clk and p is registered.
this models the power arithmetic pipeline only. The samplers, the disturbance recorder, and the feeder hardware are out of scope.
The template contains the shipped single-cycle implementation: restructure it into two pipeline stages. The latency contract is exact, so a design with one or three stages fails the bench no matter how short its longest path is. Measured with this platform's synthesis flow, the shipped code runs 33 logic levels on the longest path. So does the version that just bolts a register onto the end. The properly balanced two-stage version runs 24. The bench cannot measure levels, only the contract, so where you put the cut is on your honor: put it where it does the work.
Do not add ports.
Click Run to execute your code. Output will appear here.