Practice

Compressor Overtemp Alarm

A large air compressor at a plastics factory has a temperature guard. Once per clock cycle, a sensor circuit compares the outlet temperature against a safe limit. The comparison is already done for you. This block receives the result as 1 bit: hot_i = 1 means over the limit.

The safety rule is simple: the alarm must fire on the 3rd over-limit sample in a row. A run of 2 can be sensor noise. A run of 3 is real overheating, and that ruins the compressor's oil.

The block in your editor shipped 11 months ago, and it has been wrong the whole time. An audit replayed old sensor logs through it and found a run of exactly 3 hot samples that never raised the alarm. Longer runs do raise it, but 1 sample late. That small delay is why nobody noticed. The engineer who wrote it has left the company.

Your task: fix the block in place so alarm_o behaves exactly as specified below. This is maintenance ticket #4417, and it has been escalated twice.

Interface

PortDirectionTypeDescription
clk_iin1 bitClock
rst_iin1 bitSynchronous reset (active high)
hot_iin1 bitOver-limit flag, one sample per cycle
alarm_oout1 bitTrip output (registered)

Behavior

TRIP RULE: alarm_o rises at the clock edge that samples the 3rd consecutive hot_i = 1. It is high during the cycle after that 3rd sample.

  • alarm_o stays high as long as hot_i keeps sampling 1
  • A hot_i = 0 sample clears the alarm at that edge and resets the consecutive count: runs of one or two hot samples never trip
  • rst_i = 1 at a clock edge clears the alarm and the count, even if hot_i is high at the same edge

What the bench checks

  • The testbench checks alarm_o on every cycle
  • One or two hot samples must never trip the alarm, and a cool sample must restart the count
  • A run of exactly three hot samples must trip on the third sample, then clear on the next cool sample
  • A six-sample hot run must hold the alarm high from the third through the sixth sample
  • Reset during an alarm must clear it even while hot_i stays high
  • After that reset, the still-high input must be counted afresh and trip again on its third sample

Constraints

TIMING: everything is synchronous to clk_i and alarm_o is a registered output.

SCOPE: this models the trip logic only; the temperature comparison is already done upstream. The sensor circuit and whatever the alarm shuts down are out of scope.

The template contains the shipped, buggy implementation: fix it in place rather than starting over.

Do not add ports.

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