Chopper Phase Generator

The truck scale at the gravel yard measures signals of a few microvolts. Its amplifier keeps those readings accurate by chopping: two banks of analog switches swap the signal path back and forth, so slow drift cancels out. The logic chip that generated the two switch drives, phi_a and phi_b, died in last week's lightning storm. The vendor closed down years ago, and the firmware is gone with them. Every load of gravel leaving the yard is billed from that scale reading.

One thing survived: a Polaroid photo, taped inside the commissioning binder since 2003. It is a scope shot of the reset line and both phase drives, annotated in pencil with cycle numbers. That photo is the specification. The recertification engineer will sign off if the new drive reproduces it exactly. The retired analog engineer left one warning: the two switch banks must never be on together. Overlapping phases create a short circuit across the input.

Your task: rebuild the drive so phi_a and phi_b match the photo exactly, cycle for cycle, with the two phases never high together.

Interface

Behavior

The scope photo is the entire behavioral spec:

cycle :    1   2   3   4   5   6   7   8   9  10  11  12
rst   : ~~~~____________________~~~~____________________
phi_a : ____~~~~____________~~~~____~~~~____________~~~~
phi_b : ____________~~~~____________________~~~~________

Sampled values, same capture:

cycle :   1   2   3   4   5   6   7   8   9  10  11  12
rst   :   1   0   0   0   0   0   1   0   0   0   0   0
phi_a :   0   1   0   0   0   1   0   1   0   0   0   1
phi_b :   0   0   0   1   0   0   0   0   0   1   0   0

How to read it:

• Each column is one clock cycle; a row's value is the signal's stable level during that cycle
• The block updates its outputs at rising clock edges
• The rst value shown in a column is what the block sampled at the rising edge that starts that cycle
• The photo ends at cycle 12 but the trace does not: the repeating pattern continues unchanged until the next reset

What the bench checks

• The testbench checks both outputs on every cycle, through cycle 12 and beyond
• In cycles 1 and 7, while rst samples high, both outputs must already be low
• In cycle 2, phi_a must already be high: the outputs are registers, and they load their first post-reset value at the same edge that samples rst low

Constraints

Do not add ports.