Pulse Stretcher

A network switch is passing traffic, yet the field complaint says the activity LEDs are dead on all 24 ports. The scope trace explains it. The packet engine marks each frame with a pulse on the link-activity signal that lasts exactly 1 clock cycle, but the LED driver misses such short pulses. A colleague who has since left pushed a hotfix, and it made things worse. His version reacted to the trigger being high instead of to it going high. So when a busy port held the trigger high, it kept restarting the pulse, and the LED stayed on continuously. Support now runs two ticket categories for the same board: "LED dead" and "LED stuck".

Your task: build the stretcher that sits between the blip and the LED driver. A rising edge of the trigger, and only a rising edge, produces exactly 4 clock cycles of output. Holding the trigger high is one event, not many. A fresh edge landing mid-pulse restarts the count, so back-to-back frames show as unbroken activity instead of a stutter.

Interface

Behavior

PULSE WIDTH: a rising edge of trig_i (a clock edge sampling trig_i = 1 when the previous sample was 0) starts a pulse. pulse_o is 1 for exactly the next 4 clock cycles, then returns to 0.

• The trigger is edge-sensitive: holding trig_i high produces one 4-cycle pulse, not a continuous one
• A new rising edge of trig_i while the pulse is active restarts the count: pulse_o stays 1 for exactly 4 more cycles from that edge
• rst_i = 1 at a clock edge clears the pulse at that edge and cancels the remaining count, even if a trigger edge arrives at the same clock edge
• A trig_i already high when rst_i is released does not start a pulse; the next pulse requires a fresh rising edge of trig_i

What the bench checks

• The testbench checks pulse_o on every cycle
• A one-cycle trigger must produce exactly four high cycles, followed by a clean low cycle
• Holding trig_i high for six cycles must not retrigger or lengthen the pulse
• A fresh trigger edge two cycles into a pulse must extend the total high time to six cycles
• Reset mid-pulse must win over a simultaneous trigger edge, and a high input across reset release must not start another pulse
• A later fresh edge must still produce a normal four-cycle pulse

Constraints

TIMING: everything is synchronous to clk_i; pulse_o changes only at clock edges.

SCOPE: this models the stretcher between the packet engine's blip and the LED driver; trig_i is already synchronous. The packet engine, the LED driver, and the LED are out of scope.

Do not add ports.