Selected Assignment

The conditional chain answers "which condition is true first?" But a lot of hardware asks a simpler question: "which exact value is on this bus?" A phase code means one of four lamp patterns; a step index means one of four coil patterns. When every choice hangs off one selector signal and the choices cannot overlap, the priority chain is the wrong shape. Selected assignment is the table form: one row per selector value, no priority to reason about.

A Table on a Wire

This lesson's example decodes a traffic-light controller's 2-bit phase code into three lamps: red, yellow, green. The cycle is the European one: green, yellow, red, then red and yellow together to say "get ready", and back to green:

with phase select
  lights <= "001" when "00",   -- green
              "010" when "01",   -- yellow
              "100" when "10",   -- red
              "110" when "11",   -- red+yellow: get ready
              "100" when others; -- anything unexpected: park on red

Read it top to bottom: "with phase as the selector, lights gets 001 when the code is 00, 010 when it's 01, ..." Each row pairs one output value with one exact selector value. The rows can't overlap (a signal holds exactly one value at a time), so there is no first-wins ordering to think about. Swap two rows and the circuit is identical. That's the practical difference from when/else: a table reads like the spec it came from, and you can check it row by row against the requirements document.

Covering Every Value

The table ends with a row the cycle never uses: "100" when others. It's not optional. A std_logic wire carries nine possible values, not two (you met 'Z' and 'X' in Port Directions and 'U' in Signals and the Logic Types). So a 2-bit selector has many more patterns than 00 through 11, and VHDL insists the table says what happens for all of them. Make the others row a safe value: for a traffic light, red.

Two Tools, One Job

Both forms build multiplexers. Choosing between them is about how the decision is shaped:

The smell to watch for: a when/else chain where every condition tests the same signal against =. That's a table wearing a chain's clothes. Rewrite it as one.

This decode-a-code shape is everywhere in real designs. Combinational Building Blocks turns it into named components (decoders, multiplexers). In Finite State Machines the code being decoded is the machine's state register; a selected assignment is a standard shape for FSM output logic.

In the Example

The example panel on the right runs the phase decoder through one full cycle: phase counts 00, 01, 10, 11, then returns to 00. Watch lights follow the table: green, yellow, red, then two lamps high at once in the red+yellow phase, and back to green. Exactly one table row applies at each step; the bus value picks it directly.

Where You Stand

This lesson closes the Fundamentals level. Count what you can do. You can describe a component's interface and hide an implementation behind it. You can declare signals of the right type and width, and compute with the full operator set. And now you can wire it all together with the three concurrent assignment forms: plain, conditional, selected. You can read and write basic HDL. Every circuit so far computes its outputs from its inputs, always, in parallel. What none of them can do is remember, and that takes a different kind of statement. Procedural Blocks opens that second domain.

Key Takeaways

• Selected assignment is the table form: one selector, exact-match rows, no priority. If every condition in a chain tests the same signal for equality, write it as a table.

• Finish every table: when others is required, and it deserves a safe value.

• Entities, signals, operators, and concurrent statements: that's the complete kit for reading and writing basic HDL. Procedural blocks open the sequential world next.