Even-Parity Link

Two boards in a rack exchange 4-bit sensor readings over a 5-wire ribbon cable. The fifth wire carries an even-parity bit: the transmitter sets it so that the whole 5-bit word always holds an even number of 1s. The receiver flags any word that breaks the promise. That is how a single flipped bit gets caught. You are building one board's endpoint: the transmit side and the receive side, as pure combinational wiring.

Interface

Behavior

• The low four bits of tx carry data unchanged; the top bit, bit 4, is the parity bit
• The parity bit is the XOR of the four data bits: 1 exactly when data holds an odd number of 1s. That is what makes the full 5-bit word always even
• parity always equals the parity bit (bit 4 of tx)
• err is high exactly when rx holds an odd number of 1s; a clean word from the far end always has an even count
• The two paths are independent: the testbench drives data and rx together and checks all three outputs on every step

Constraints

• Compute the parity bit once: give it an internal signal and let both tx and parity read it