Even-Parity Link

Two boards in a rack exchange 4-bit sensor readings over a 5-wire ribbon cable. The fifth wire carries an even-parity bit: the transmitter sets it so that the whole 5-bit word always holds an even number of 1s. The receiver flags any word that breaks the promise. That is how a single flipped bit gets caught. You are building one board's endpoint: the transmit side and the receive side, as pure combinational wiring.

Interface

Behavior

• The low four bits of tx_o carry data_i unchanged; the top bit, bit 4, is the parity bit
• The parity bit is the XOR of the four data bits: 1 exactly when data_i holds an odd number of 1s. That is what makes the full 5-bit word always even
• parity_o always equals the parity bit (bit 4 of tx_o)
• err_o is high exactly when rx_i holds an odd number of 1s; a clean word from the far end always has an even count
• The two paths are independent: the testbench drives data_i and rx_i together and checks all three outputs on every step

Constraints

STRUCTURE: assignment outside a procedural blocks only; no procedural blocks.

• Compute the parity bit once: give it an internal signal and let both tx_o and parity_o read it
• Reading parity_o back inside the design is legal and produces the same hardware, so the testbench cannot distinguish that shortcut. The internal signal is on your honor: it is the reuse pattern this exercise asks you to practise