Repack the Telemetry Word

A telemetry receiver hands you raw 16-bit words from a weather probe. The wire format packs four fields:

Downstream units want the word taken apart and partly reassembled. The 8-bit sample goes to the display driver as-is, and the valid flag is needed on its own wire. The logger wants a compact header byte: valid flag on top, then the channel, then the sequence counter, with the sample dropped.

This is selection only. No gates, no arithmetic, pure wiring. The two languages build the header differently, each in its own idiom:

• VHDL: drive header slice by slice with separate concurrent assignments; disjoint slices are one driver per wire.
• SystemVerilog: build the byte in one assign with the {} glue, MSB first. One variable, one defining expression.

Interface

Declarations: VHDL, std_logic_vector(15 downto 0) for raw, std_logic_vector(7 downto 0) for the byte outputs, std_logic for valid; SystemVerilog, logic [15:0], logic [7:0], and logic.

Behavior

• valid follows bit 15 of raw
• sample follows bits 11..4 of raw
• header carries: bit 7 = the valid flag, bits 6..4 = the channel (raw bits 14..12), bits 3..0 = the sequence counter (raw bits 3..0)
• Pure combinational wiring: every output follows raw immediately

The testbench probes single set bits at the field boundaries (bits 15, 12, 11, 4, and 3). An off-by-one slice puts a bit in the wrong place, and the failure message names the boundary that leaked.

Constraints

• VHDL: three separate assignments build header's slices; SystemVerilog: a single assign builds the whole header