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Sign Extension and Overflow Flags

A temperature sensor delivers 4-bit two's complement readings, but the processing datapath is 8 bits wide and its adder needs an overflow flag. You are wiring the datapath's signed support unit: widen the reading correctly, expose its sign, and judge overflow from three sign bits. No arithmetic anywhere, only wiring and gates.

This module contains two independent pieces of logic. First, sign-extend the sensor reading a_i and expose its sign. Separately, assume an external adder has already added two operands. It supplies only the sign bits of operand A, operand B, and the result through s_a_i, s_b_i, and s_sum_i. No addition is performed in this module; use those three bits to detect signed overflow.

Interface

PortDirectionTypeDescription
a_iin4-bit vector4-bit two's complement sensor reading
ext_oout8-bit vectorThe reading, sign-extended to 8 bits
neg_oout1 bitHigh when the reading is negative
s_a_iin1 bitSign bit of the adder's operand A
s_b_iin1 bitSign bit of the adder's operand B
s_sum_iin1 bitSign bit of the adder's result
ovf_oout1 bitHigh when the addition overflowed

Behavior

  • ext_o carries the same signed value as a_i: the low four bits pass through. Each of the four new upper bits is a copy of a_i's sign bit
  • neg_o is exactly a_i's sign bit
  • ovf_o is high when both operand signs agree and the result's sign differs from them
  • Opposite operand signs never overflow: ovf_o stays low whenever s_a_i and s_b_i differ

The testbench checks sign extension on positive and negative readings, then sweeps all eight sign-bit combinations.

Constraints

OPERATORS: only bit selection, concatenation, and the gates and, or, and not; no arithmetic operators and no comparisons.

  • Leave xor out for this gate-expression practice. Derive the overflow expression from the sign combinations that cannot represent a correct sum.

  • One assignment outside a procedural block per output

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