Silo RS485 Burst

Longbarrow Silo's level controller talks to the yard office over a two-wire RS-485 cable beside the weighbridge. The link is half duplex.

Its transceiver drives the line only while its driver-enable pin is high.

The shipped controller dropped driver enable as soon as the last data bit went out. The final stop bit was still crossing the long cable.

The office radio clicked on the chopped last byte, so every third command had to be sent twice.

Your task: build a burst transmitter that owns the line a little early and lets go a little late. Send all three command bytes without gaps. Keep the driver on through the full last stop bit and a short tail.

Interface

Behavior

• The unit listens for start_i only between bursts; an accepted request opens its burst on the next clock
• Acceptance latches payload_i on the spot
• A burst in flight keeps that latched copy, whatever payload_i does afterwards
• While busy_o is high, every further start_i pulse is ignored
• busy_o goes high at acceptance and remains high through the final tail clock
• The UART format is 8N1, with four clocks for every bit
• Each byte has one low start bit, eight data bits, and one high stop bit
• Data bits are sent least significant bit first
• payload_i[7:0] is sent first, followed by payload_i[15:8], then payload_i[23:16]
• Each burst starts with exactly four lead clocks
• During all four lead clocks, de_o is high and tx_o remains high
• The three bytes follow the lead period back to back
• There are no extra idle clocks between one byte's stop bit and the next byte's start bit
• After the third byte's full stop bit, the burst has exactly four tail clocks
• During all four tail clocks, de_o remains high and tx_o remains high
• de_o is high for every burst clock, including the whole final stop bit and the whole tail
• done_o pulses exactly once, on the final tail clock
• busy_o is still high during the done_o pulse
• After the final tail clock, de_o and busy_o fall together, and the unit becomes idle
• While idle, tx_o is high, de_o is low, and both status outputs are low
• rst_i high at any rising edge releases the line, clears both status outputs, and aborts all burst progress
• After reset, tx_o is high, de_o is low, and no aborted burst resumes

What the bench checks

• The testbench checks idle acceptance, next-clock burst start, and ignored requests while busy
• It changes payload_i during a burst and checks that the captured payload remains in use
• A bench-side decoder rebuilds all three bytes from tx_o alone, checking framing, bit width, byte order, and gapless frames
• It checks exactly four lead clocks and exactly four tail clocks, with de_o and tx_o high through both
• Releasing de_o during the final stop bit or anywhere in the tail fails
• It asserts reset during lead, data, stop, and tail clocks

Constraints

TIMING: everything is synchronous to clk_i; inputs are sampled on rising edges, and all outputs are registered.

SCOPE: this models the transceiver's tx_o and driver-enable logic pins only. It does not model A/B differential signals, cable reflections, or receive direction.

Do not add ports.