Practice
Packing Camera Capture
At Fenwick Mail Centre, a small camera photographs every box above belt 6. It sends each pixel as two bytes over an 8-bit parallel bus.
One damaged image line arrived one byte short. The old capture block missed the fault, so every colour after it shifted by one byte.
On the preview screen, orange packing tape turned blue halfway across each box.
The error lasted until someone powered the sorter off and on. Boxes kept moving, but their saved images could not be trusted.
Your task: build the camera capture stage. Pair bytes again at every line, publish complete RGB565 pixels, and report any line that ends with half a pixel.
Interface
| Port | Direction | Type | Description |
|---|---|---|---|
pclk | in | 1 bit | Pixel clock from the camera and the only DUT clock |
rst | in | 1 bit | Synchronous reset (active high) |
vsync | in | 1 bit | Frame separator, high between frames while href is low |
href | in | 1 bit | High while a line's bytes stream |
d | in | 8-bit vector | One byte per clock while href is high |
pixel | out | 16-bit vector | Last completed RGB565 pixel, held |
pixel_valid | out | 1 bit | Completed pixel (one-pclk pulse) |
frame_start | out | 1 bit | First captured byte of a frame (one-pclk pulse) |
line_end | out | 1 bit | Line closed (one-pclk pulse) |
frame_err | out | 1 bit | Line closed on a half pixel (one-pclk pulse) |
Behavior
- The camera changes
vsync,href, anddafter fallingpclkedges - The capture stage samples all inputs only on rising
pclkedges - While
hrefis high, every rising edge carries one byte - Each RGB565 pixel contains two bytes, with the high byte first
- Nothing is captured while
hrefis low orvsyncis high - Each sampled low-to-high transition on
hrefresets byte pairing - Every line therefore starts with a high byte, regardless of the previous line
- One clock after a pixel's second byte is sampled,
pixelupdates andpixel_validpulses pixelholds its value between completed pixelspixel_validis low except during its one-pclk pulses- Each observed
vsyncpulse marks the next captured line as the first line of a new frame frame_startpulses one clock after that line's first byte is sampledframe_startpulses only once per frame- When
hreffalls after an even byte count,line_endpulses one clock later - When
hreffalls after an odd byte count,line_endandframe_errpulse together one clock later - A half pixel at the end of a damaged line is discarded and never published
- The next line starts fresh with high-byte-first pairing
- After reset, capture stays idle until a
vsyncpulse has been observed, andpixelreads zero until the first published pixel - Any lines seen before the first
vsyncpulse are ignored rsthigh at a rising edge clears capture progress and returns the stage to its initial waiting statepixel,pixel_valid,frame_start,line_end, andframe_errare registered outputs
What the bench checks
- The testbench changes camera inputs after falling edges and checks every output cycle by cycle against a reference model
- It sends byte patterns that expose swapped, shifted, or wrongly paired bytes, with the first byte expected in bits 15 through 8
- It sends an odd-length line and checks that
line_endandframe_errpulse together one clock after the fall - It checks that the dangling half pixel is discarded and never reaches
pixel - It follows the damaged line with a clean one and checks that pairing re-anchors on the
hrefrise - It sends lines before the first
vsyncpulse and checks that they are ignored - It resets mid-line with a pixel one clock from publishing and checks that nothing of that line comes out
Constraints
everything is synchronous to pclk; camera inputs change after falling edges, capture samples only on rising edges, and all outputs are registered.
this models the digital capture contract on the pixel clock. Input-delay constraints, the sensor's analog side, and moving pixels into another clock domain are out of scope.
Do not add ports.
Click Run to execute your code. Output will appear here.