Tremor Mark Crossing

The earthquake monitoring station at Cinder Ridge has two boards, and they run on two different clocks. The digitizer board samples the ground sensor every 10 ns. The logger board writes event marks into the record, and it runs on its own 16 ns clock.

The old design wired the trigger mark straight from one board to the other. That fails, because a 10 ns pulse can fall entirely between two edges of the 16 ns clock. Depending on how the two clocks happened to line up, a mark was sometimes lost and sometimes recorded twice. One doubled mark woke the duty seismologist at 3 a.m. for an earthquake swarm that never happened.

Your task: build the block that carries each mark safely from the digitizer clock to the logger clock. Every mark_a_i pulse must produce exactly 1 pulse on mark_b_o: never 0, never 2. Each mark_b_o pulse must be exactly 1 logger cycle wide. Marks arrive at least 5 digitizer cycles apart, and the testbench sends bursts at exactly that spacing. The two clocks cannot be synchronized, so your design must work for every possible alignment.

Interface

Behavior

• mark_a_i is high for exactly one clk_a cycle per event
• Marks arrive at least 5 clk_a cycles apart, start to start
• Every mark_a_i pulse must produce exactly one mark_b_o pulse: never zero, never two
• Each mark_b_o pulse is exactly one clk_b cycle wide; mark_b_o changes only at clk_b rising edges and is 0 between marks
• A mark crosses within four clk_b cycles of its mark_a_i pulse
• The clocks are 10 ns and 16 ns. Do not rely on any fixed alignment between them
• rst_a_i and rst_b_i are asserted together at power up, held for several cycles of each clock, and released while mark_a_i is quiet
• After reset release mark_b_o stays 0 until the first mark arrives; neither reset is used again

What the bench checks

• The testbench drives bursts at exactly the minimum spacing of 5 clk_a cycles, start to start
• The testbench allows six clk_b cycles before it audits the counts
• The testbench drifts the clock phase across the whole common period, so marks land at every alignment the 10 ns and 16 ns clocks can produce
• The testbench counts marks sent against marks received after every test phase, checks the one-cycle width at every clk_b cycle, and verifies long quiet stretches stay quiet
• It also times every mark: mark_b_o must rise within four clk_b cycles of the clk_a edge that captured the mark

Constraints

TIMING: there is no single clock here: digitizer-side logic is synchronous to clk_a_i, logger-side logic to clk_b_i, and mark_b_o changes only at clk_b_i rising edges.

SCOPE: this models one trigger mark's crossing between the two board clocks, with marks at least 5 clk_a_i cycles apart. The ground sensor, the digitizer's sampling, and the log record format are out of scope.

CLOCK DOMAINS: everything on the logger side of the crossing is clocked by clk_b_i only, and everything on the digitizer side by clk_a_i only. There is no combinational path from mark_a_i to mark_b_o.

SYNCHRONIZER: any signal leaving the digitizer domain must pass through at least two clk_b flip-flops before it feeds logger-side logic.

The simulator cannot detect a missing synchronizer stage. The bench enforces what it can measure: mark counts, pulse width, and timing. The two-stage rule is part of the contract regardless. Do not add ports.