Roller Rink Fader

VERIFIED LIVE SCORE: Best 386 cells (SystemVerilog) from 8 passing runs. Budget: 500 cells or fewer. 4 of 5 registered participants solved it.

The Starlite roller rink runs its light-and-sound show from one aging FPGA, and the last build came out 97 percent full. The one new feature the owner asked for this year is a stereo balance fader, so the announcer's microphone can follow a birthday party around the rink.

The block itself is small. It takes one 8-bit audio sample and two 8-bit gain knobs. It outputs two products to the DAC card (the board that turns numbers back into sound): left_o = sample_i * gain_l_i and right_o = sample_i * gain_r_i. The intern wrote exactly that, one multiplier per channel. The result does not fit the 500-cell budget, and the mirror-ball motor controller is not getting smaller to make room.

The DAC card's contract gives you the opening: the card reloads its registers slowly, so nobody needs fresh products on the very next edge. The Behavior section grants a 2-edge settle window.

Your task: produce the same two products with 500 cells or fewer. The live score panel above is generated from verified passing runs, so the record moves when somebody genuinely beats it.

Interface

Behavior

• Both outputs are registers; after a reset edge both read 0
• Whenever sample_i, gain_l_i and gain_r_i are unchanged at two consecutive rising edges, left_o and right_o must equal the two products from the second of those edges onward
• The outputs then hold steady while the inputs hold
• While the inputs are changing, the outputs are unconstrained until the two-edge settle has elapsed
• Products are plain unsigned 8x8 multiplication into 16 bits, no rounding, no saturation
• rst_i = 1 at a rising edge clears both outputs to 0, whatever was in flight; after release the settle rule applies as usual

What the bench checks

• The testbench never checks inside the settle window
• Directed holds cover silence, centered gain, hard-left and hard-right settings, muted output, low values, asymmetry, and full-scale multiplication
• Thirty pseudo-random input sets are each held for four cycles, with both products checked after the first two edges
• Reset mid-run must clear both outputs immediately, followed by a correctly settled directed result

Constraints

TIMING: everything is synchronous to clk_i and both outputs are registered.

SCOPE: this models the two gain products and nothing else. The microphone chain and the DAC card are out of scope; the 2-edge settle window comes from the card's reload contract.

CELL BUDGET: 500 cells or fewer, as counted by the Netlist tab's stats bar after you run your design.

The behavioral testbench and synthesis budget are both enforced by the run service. A design only becomes a verified passing run when it satisfies both.

Do not add ports.