Pressure Rig DAC Staircase

Bracken Gauge Works uses a pressure calibration rig to check rows of brass-faced gauges. A 12-bit parallel DAC feeds a reference sensor with a steady test level.

The DAC datasheet is strict. The data pins must settle before the write strobe rises. They must also remain stable after that edge.

The shipped sequencer changed the code as it raised the strobe. The DAC caught half-changed values, so the reference voltage skipped steps on its way up.

Red pen marks covered the bent curves on the morning's calibration sheets.

Your task: build a stepper that walks from zero to full scale. Give every code four clocks, and treat the DAC timing rules as law.

Interface

Behavior

• A request from start_i is accepted only while idle, and its staircase begins on the next clock
• step_i is captured at acceptance
• Later changes to step_i do not affect a running staircase
• Any start_i assertion while busy_o is high is ignored
• busy_o goes high at acceptance and remains high through the final dwell's last clock
• A captured step_i of zero counts as one
• The first emitted code is zero
• Each later code adds the captured effective step to the previous code
• The final emitted code is always exactly 0xFFF
• An addition that would pass 0xFFF saturates to 0xFFF
• The code 0xFFF is emitted once and only once, as the staircase's last code
• Every code has a fixed four-clock dwell, and consecutive dwells run back to back
• On dwell clock 1, dac_data_o takes the new code while wr_n_o is high
• On dwell clock 2, wr_n_o goes low while dac_data_o holds the code
• On dwell clock 3, wr_n_o returns high while dac_data_o still holds the code
• On dwell clock 4, wr_n_o remains high and dac_data_o still holds the code
• The DAC latches on the rising edge of wr_n_o, which occurs on dwell clock 3
• dac_data_o is stable from the clock before that edge through the clock after it
• done_o pulses for exactly one clock, on dwell clock 4 of the final code
• busy_o remains high during the done_o pulse
• On the next clock, busy_o and done_o fall together, and the unit becomes idle
• While idle, wr_n_o is high, and both status outputs are low
• rst_i high at any rising edge sets dac_data_o to zero, raises wr_n_o, clears both status outputs, and returns the unit to idle
• Reset cancels all staircase progress, and nothing resumes afterward

What the bench checks

• The testbench checks idle acceptance, next-clock startup, captured step_i, and ignored requests while busy
• It checks code order with steps that advance normally, equal zero, land on 0xFFF, or pass it
• It checks that every staircase starts at zero and emits 0xFFF exactly once
• It checks all four dwell clocks cycle by cycle, including data stability around the rising wr_n_o edge
• It checks the final done_o pulse while busy_o remains high, followed by their shared falling edge
• It asserts reset during different dwell phases and checks that no cancelled staircase resumes

Constraints

TIMING: everything is synchronous to clk_i; inputs are sampled on rising edges, and all outputs are registered.

SCOPE: this models the DAC's digital pins and timing contract. The analog output, reference, and settling are out of scope.

Do not add ports.