Fountain Stagger

VERIFIED LIVE SCORE: Best 4 FFs (SystemVerilog) from 3 passing runs. Budget: 6 FFs or fewer. 2 of 3 registered participants solved it.

The Marchetti fountain has 4 pump groups: the perimeter jets, two arc rings, and the center plume. Each group starts through a contactor (a heavy relay that switches the pump motor). The contactors used to close on the same clock cycle. Four motors starting at once tripped the plaza's feed breaker about one morning in five. The city electrician's report is one sentence: start them 4 counts apart and the breaker holds.

Here is the catch. The show controller is a small programmable logic chip (a CPLD) with 6 spare macrocells, and in this chip family one macrocell means one flip-flop. The obvious design, a chain of delay stages with one flip-flop per count, synthesizes to 13 flip-flops. It does not fit.

Your task: build the staggered starter in 6 flip-flops or fewer. When go_i rises, en_o(0) starts first, and en_o(1), en_o(2), en_o(3) join at 4-count intervals. Everything stays on while go_i stays high. The go_i line is also the dead-man switch, the line that must stay high for anything to run. Every contactor must release the moment go_i drops, not a clock cycle later, and the next start replays the whole stagger. The live score panel above is generated from verified passing runs.

Interface

Behavior

• Call cycle 1 the first full clock cycle after go_i is sampled high at a rising edge
• en_o(0) is high during cycle 1 and every following cycle while go_i stays high
• en_o(1) joins from cycle 5, en_o(2) from cycle 9, en_o(3) from cycle 13, each staying high while go_i holds
• Once all four are on, the pattern holds steady for as long as go_i stays high, however long that is
• When go_i goes low, all four enables are low by the next check, and the stagger starts over on the next assertion of go_i
• A one-cycle dropout of go_i restarts the full sequence
• rst_i = 1 at a rising edge clears the stagger timer; during that cycle en_o(0) follows go_i and the other three enables are low
• The reset cycle does not advance the sequence: with go_i held high, the full stagger replays, counted from the first edge after rst_i falls

What the bench checks

• The testbench checks all four enables on every cycle
• The testbench drives full ramps, long holds, dead-man drops from every phase, a one-cycle go_i blip, and a reset in mid-ramp
• After every drop of go_i it also probes the enables between clock edges: a release that waits for the next edge fails

Constraints

TIMING: the stagger counting is synchronous to clk_i. The dead-man release is not: a dropped go_i must reach the enables without waiting for a clock edge.

SCOPE: this models the enable logic for the four contactors. The contactors themselves, the pump motors, and the plaza's feed breaker are out of scope.

FF BUDGET: 6 flip-flops or fewer as reported by the Netlist tab FFs stat after synthesis (the delay-chain draft measures 13).

The enables may be plain combinational decode. The behavioral testbench and synthesis budget are both enforced by the run service. A design only becomes a verified passing run when it satisfies both.

Do not add ports.