RisingEdge
.pro
Playground
Try the challenges
VHDL
SV
SystemVerilog
▶ Run
Top
Target
Gates
LUT4
LUT6
iCE40
ECP5
Xilinx
coarse cells (no ABC)
Testbench
user_design.vhd
testbench.vhd
+
+ Add files
Loading editor...
Netlist
Run to see the schematic
Waveform
Logs
⤢
Click Run to execute your code. Output will appear here.