library ieee;
use ieee.std_logic_1164.all;

entity example is
  port (
    clk_i : in  std_logic;
    rst_i : in  std_logic;
    d_i   : in  std_logic;
    q_o   : out std_logic
  );
end entity example;

architecture rtl of example is
begin
  process(clk_i, rst_i)
  begin
    if rst_i = '1' then
      q_o <= '0';
    elsif rising_edge(clk_i) then
      q_o <= d_i;
    end if;
  end process;
end architecture rtl;